FIG. 1 is a schematic view of a conventional LCD apparatus. Referring to FIG. 1, the conventional LCD apparatus comprises a display panel 110, a printed circuit board 120 and a flexible printed circuit board 130. The display panel 110 has a display region 112 in which a plurality of pixels (not shown) and a plurality of scan lines are formed. Furthermore, a plurality of scan drivers (for example, three scan drivers labeled by 114, 116 and 118 are shown herein) are disposed in an outer frame (not labeled) of the display panel 110, so that the scan drivers can output scan pulses (not labeled, and it will be described later) to the scan lines in the display region 112 to turn on the corresponding pixels and load display data respectively.
The printed circuit board 120 comprises a shading signal generating circuit 122, a power supplying circuit 124 and a time-sequence control circuit 126. The shading signal generating circuit 122, the power supplying circuit 124 and the time-sequence control circuit 126 are configured for generating a shading signal VGHM, a logic low potential VGL and an output enable signal OE for each of the scan drivers. The shading signal VGHM, the logic low potential VGL and the output enable signal OE are all transmitted to the scan driver 118 through the flexible printed circuit board 130, then the scan driver 118 transmits the received shading signal VGHM, the received logic low potential VGL and the received output enable signal OE to the scan driver 116, and finally the scan driver 116 transmits the received shading signal VGHM, the received logic low potential VGL and the received output enable signal OE to the scan driver 114. After each of the scan drivers receives the shading signal VGHM, the logic low potential VGL and the output enable signal OE, each of the scan drivers generates the needed scan pulses according to the received shading signal VGHM, the received logic low potential VGL and the received output enable signal OE.
FIG. 2 is a circuit schematic view of the shading signal generating circuit shown in FIG. 1. Referring to FIG. 2, the shading signal generating circuit 122 comprises a positive-charge pump 202, an inverter 204, a P-type transistor 206, an N-type transistor 208, a resistor 210 and a capacitor 212. A terminal of the resistor 210 and a terminal of the capacitor 212 are electrically coupled to the ground potential GND. In addition, the positive-charge pump 202 is configured for providing a logic high potential VGH. An input terminal of the inverter 204 is configured for receiving a duty-cycle control signal CTL, and a node Q where the P-type transistor 206, the N-type transistor 208 and the capacitor 212 are coupled to each other is configured for outputting the shading signal VGHM. FIG. 3 is a schematic view for showing waves of the duty-cycle control signal and the shading signal shown in FIG. 2. Referring to FIGS. 2 and 3, when the duty-cycle control signal CTL is at the high potential, the P-type transistor 206 is turned on. Therefore, the positive-charge pump 202 can charge the capacitor 212 through the P-type transistor 206, so as to pull up the potential at the node Q to the logic high potential VGH. When the duty-cycle control signal CTL is at the low potential, the N-type transistor 208 is turned on. Therefore, the capacitor 212 is electrically coupled to the ground potential GND through the N-type transistor 208 and the resistor 210 to discharge the charges of the capacitor 212, so that the potential at the node Q is gradually reduced. Therefore, the shading signal VGHM is formed.
FIG. 4 is a schematic view for showing a time-sequence relation between a scan pulse generated by the scan drivers and the output enable signal. Referring to FIG. 4, the scan pulse GP is formed according to the shading signal VGHM, the logic low potential VGL and the output enable signal OE, and the output enable signal OE is configured for compulsorily pulling down the potential of the scan pulse GP to the logic low potential VGL. Therefore, it can use the shaded scan pulse GP to drive the scan lines of the display panel 110, so as to improve the image flicker caused by the feed-through effect.
However, since the scan drivers are disposed in different positions of the display panel 110, the signal-transmitting paths for transmitting the output enable signal OE to the scan drivers are different from each other. Therefore, the scan drivers will receive the output enable signal OE with different delay degrees, so that the scan pulses generated by the scan drivers are pulled down to different potentials respectively before they are compulsorily pulled down to the logic low potential VGL. FIG. 5 is a schematic view for showing three different scan pulses. Referring to FIG. 5, a scan pulse G1 is generated by the scan driver 118, a scan pulse G2 is generated by the scan driver 116, and a scan pulse G3 is generated by the scan driver 114. When the scan driver 118 receives the output enable signal OE, the output enable signal OE is delayed with a minimum degree. Thus, the scan pulse G1 generated by the scan driver 118 will be compulsorily pulled down to the logic low potential VGL by the output enable signal OE before the scan pulse G1 is pulled down to 19V. On the contrary, when the scan driver 114 receives the output enable signal OE, the output enable signal OE is delayed with the maximum degree. Thus, the scan pulse G3 generated by the scan driver 114 will be compulsorily pulled down to the logic low potential VGL by the output enable signal OE when the scan pulse G3 is pulled down to 15V.
Since the scan pulses generated by the scan drivers are pulled down to different potentials before they are compulsorily pulled down to the logic low potential VGL, it does not favor the improvement of the image flicker.